Sunday October 9, 2011
17.00-18.00					CONFERENCE REGISTRATION
18.00-19.00					RECEPTION
		Monday October 10, 2011
08:00-08:30					WELCOME COFFEE CONFERENCE REGISTRATION
08:30-08:45					WELCOME by Georgi Gaydadjiev and Sofiene Tahar (AUDITORIUM)
08:45-09:45					KEYNOTE PRESENTATION 1 (AUDITORIUM)
					Srini Devadas, MIT
					Memory Coherence in Multicore Age
09:45-10:00					COFFEE BREAK
10:00-11:40		Session 1.1 Networks on Chip (Systems Track) Session Chair: Greg Byrd, NC State Univ.	10:00-11:40		Session 1.2 Energy-Efficient Architectures (Architecture Track) Session Chair: Ramon Canal, UPC	10:00-11:40		Session 1.3 Recent Advances in EDA (EDA Track) Session Chair: Kaijie Wu, Univ. Illinois at Chicago
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1		PAPER ID	ROOM 2
10:00-10:25	199	A GALS Network-on-Chip Based on Rationally-Related Frequencies	10:00-10:25	227	DPPC: Dynamic Power Partitioning and Capping in Chip Multiprocessors	10:00-10:25	55	Pre-Assignment RDL Routing via Extraction of Maximal Net Sequence
	REGULAR	J. Chabloz, A. Hemani		REGULAR	K. Ma, X. Wang, Y. Wang		REGULAR	J. Yan, Z. Chen
10:25-10:50	63	EM and Circuit Co-Simulation of a Reconfigurable Hybrid Wireless NoC on 2D Ics	10:25-10:50	174	A Machine Learning Approach to Modeling Power and Performance of Chip Multiprocessors	10:25-10:50	125	Path Aware Event Scheduler in HoldAdvisor for Fixing Min Timing Violations
	REGULAR	A. More, B. Taskin		REGULAR	C. Zhang, A. Ravindran, K. Datta, A. Mukherjee, B. Joshi		REGULAR	T. Xiao, G. Chen, H. Bagga, B. Tutuianu, R. Pattipati, M. Shnur, R. Chung, R. Cheung
10:50-11:15	116	Leveraging Torus Topology with Deadlock Recovery for Cost-Efficient On-Chip Network	10:50-11:15	64	Using Content-Aware Bitcells to Reduce Static Energy Dissipation	10:50-11:15	45	A Tool Set for the Design of Asynchronous Circuits with Bundled-Data Implementation
	REGULAR	M. Shin, J. Kim		REGULAR	F. Koc, O. Simsek, O. Ergin		REGULAR	M. IIzuka, N. Hamada, H. Saito, R. Yamaguchi, M Yoshinaga
11:15-11:40	248	A Dynamic and Distributed TDM Slot-Scheduling Protocol for QoS-Oriented Networks-on-Chip	11:15-11:40	117	Tree Structured Analysis on GPU Power Study	11:15-11:40	29	Applying Verification Intention for Design Customization via Property Mining under Constrained Testbenches
	REGULAR	N. Concer, A. Vesco, R Scopigno, L. Carloni		REGULAR	J. Chen, B. Li, Y. Zhang, L Peng, J. Peir		REGULAR	C. Chung, C. Chang, K. Chang, S. Kuo
11:40-15:30					SOCIAL EVENT
15:30-16:00					COFFEE BREAK
16:00-17:40		Session 2.1 Test and Verification Session Chair: Sule Ozev, Arizona State Univ.	16:00-17:40		Session 2.2 Microarchitectural Techniques (Architecture Track) Session Chair: Michael Gschwind, IBM	16:00-17:40		Session 2.3 Memristor and Signal Processing (Logic and Circuits Track) Session Chair: David Penry, Brigham Young Univ.
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1		PAPER ID	ROOM 2
16:00-16:25	283	Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores	16:00-16:25	204	An Optimized Scaled Neural Branch Predictor	16:00-16:25	4	Memristor-Based IMPLY Logic Design Flow
	REGULAR	D. Lewis, S. Panth, X. Zhao, S. Lim, H. Lee		REGULAR	D. Jimenez		REGULAR	S. Kvatinsky, E. Friedman, A. Kolodny, U. Weiser
16:25-16:50	126	Reduced Complexity Test Generation Algorithms for Transition Fault Diagnosis	16:25-16:50	23	TAP Prediction: Reusing Conditional Branch Predictor for Indirect Branches with Target Address Pointers	16:25-16:50	122	A Memristor-Based Memory Cell using Ambipolar Operation
	REGULAR	Y. Zhang, V. Agrawal		REGULAR	Z. Xie, D. Tong, M. Huang, X. Wang, Q. Shi, X. Cheng		REGULAR	F. Lombardi, P. Junsangsri
16:50-17:15	144	Enhanced Symbolic Simulation of a Round-Robin Arbiter	16:50-17:15	178	Simultaneous Continual Flow Pipeline Architecture	16:50-17:15	78	Using Stochastic Computing to Implement Digital Image Processing Algorithms
	REGULAR	Y. Li, N. Zeng, W. Hung, X. Song		REGULAR	K. Jothi, M. Sharafeddine, H. Akkary		REGULAR	P. Li, D. Lilja
17:15-17:40	143	Using Analog Circuit Behavior to Generate SystemC Events for an Acceleration of Mixed-Signal Simulation	17:15-17:40	7	Thread-Aware Dynamic Shared Cache Compression for Multicore Processors	17:15-17:40	70	A Simple Pipelined Squaring Circuit for DSP
	REGULAR	S. Hoelldampf, D. Zaum, M. Olbrich, E. Barke		REGULAR	Y. Xie, G. Loh		REGULAR	V. Risojevic, A. Avramovic, Z. Babic, P. Bulic
17:40					END OF THE SESSIONS
		Tuesday October 11, 2011
08.00-08.30			WELCOME COFFEE
08.30-09.30			KEYNOTE PRESENTATION 2 (AUDITORIUM)
			Joel Emer, Intel
			Addressing the General Purpose Processor Dilemma with Reconfigurable Logic Computing
09:30-09:45			COFFEE BREAK
09:45-11:50		Session 3.1 Energy- and Thermal-Aware Design (Systems Track) Session Chair: Omer Khan, MIT	09:45-11:25		Session 3.2 Reversible Logic and Special Arithmetic Blocks (Logic and Circuits Track) Session Chair: Jun Yuan, Cadence
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1
09:45-10:10	22	AURA: An Application and User Interaction Aware Middleware Framework for Energy Optimization in Mobile Devices	09:45-10:10	90	A Study on Relating Redundancy Removal in Classical Circuits to Reversible Mapping
	REGULAR	B. Donohoo, C. Ohlsen, S. Pasricha		REGULAR	S. Sultana, Y. Pang, K. Radecka
10:10-10:35	136	Energy-Efficient Multi-Level Cell Phase-Change Memory System with Data Encoding	10:10-10:35	164	Positive Davio-Based Synthesis Algorithm for Reversible Logic
	REGULAR	J. Wang, X. Dong, G. Sun, D. Niu, Y. Xie		REGULAR	Y. Pang, S. Wang, Z. He, J. Lin, S. Sultana, K. Radecka
10:35-11:00	183	Distributed Thermal Management for Embedded Heterogeneous MPSoCs with Dedicated Hardware Accelerators	10:35-11:00	48	Special-Purposed VLIW Architecture for IEEE-754 Quadruple Precision Elementary Functions on FPGA
	REGULAR	Y. Wu, S. Sharifi, T. Rosing		REGULAR	L. Yuanwu
11:00-11:25	241	Energy-Aware Standby-Sparing Technique for Periodic Real-Time Applications	11:00-11:25	62	Fast and Compact Binary-to-BCD Conversion Circuits for Decimal Multiplication
	REGULAR	M. Haque, H. Aydin, D. Zhu		REGULAR	O. Al-Khaleel, Z. Al-Qudah, M. Al-Khaleel, C. Papachristou, F. Wolff
11:25-11:50	149	A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multi-Core Embedded Systems
	REGULAR	A. Munir, A. Gordon-Ross, S. Ranka
11:50-13:00			LUNCH
13:00-14:00			PANEL: Challenges in Computing in the Age of Heterogeneous Platforms
14:00-14:15			COFFEE BREAK
14:15-15:05		Session 4 Best Papers Session Chairs: Georgi Gaydadjiev, TU Delft and Sofiene Tahar, Concordia University
	PAPER ID	AUDITORIUM
14:15-14:40	16	RoShaQ: High-Performance On-Chip Router with Shared Queues
	REGULAR	A. Tran, B. Baas
14:40-15:05	89	Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC
	REGULAR	S. Rethinagiri, R. Atitallah, S. Niar, E. Senn, J. Dekeyser
15:05-15:20			COFFEE BREAK
15:20-16:35		Session 5.1 New Techniques for System-Level Simulation and Optimization (EDA Track) Session Chair: Alodeep Sanyal, Synopsys	15:20-16:35		Session 5.2 Topology and Physical Design (Logic and Circuits Track) Session Chair: Fabrizio Lombardi, Northeastern Univ.
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1
15:20-15:45	254	Video Quality-Driven Buffer Dimensioning in MPSoC Platforms via Prioritized Frame Drops	15:20-15:45	130	A Novel Shared-Buffer Router for Network-on-Chip Based on Hierarchical Bit-Line Buffer
	REGULAR	D. Gangadharan, M. Haiyang, S. Chakraborty, R. Zimmerman		REGULAR	W. Shi, H. Ren, Q. Dou, Z. Wang, L. Shen, C. Liu
15:45-16:10	157	Techniques for LI-BDN Synthesis for Hybrid Microarchitectural Simulation	15:45-16:10	215	ROA-Brick Topology for Rotary Resonant Clocks
	REGULAR	T. Harris, Z. Ruan, D. Penry		REGULAR	Y. Teng, J. Lu, B. Taskin
16:10-16:35	13	Runtime Adaptable Concurrent Error Detection for Linear Digital Systems	16:10-16:35	93	Impact and Optimization of Lithography-Aware Regular Layout in Digital Circuit Design
	REGULAR	Y. Liu, K. Wu		REGULAR	V. Dal Bem, P. Butzen, F. Marranghello, A. Reis, R. Ribas
16:35-17:00			COFFEE BREAK
17:00-18:30			POSTER SESSION
18:30			END OF THE SESSIONS
19:00-22:00			GALA DINNER
			KEYNOTE PRESENTATION 3 (DURING GALA DINNER)
			David Kaeli, Northeastern Univ.
			The Convergence of HPC and Embedded Systems in our Heterogeneous Computing Future
		Wednesday October 12, 2011
08.00-08.30			WELCOME COFFEE
08.30-11:25		Session 6 Special Session on Hardware Trust: Capture the Chip Session Chairs: Sule Ozev, Arizona State University and Russell Tessier, University of Massachusetts
	PAPER ID	AUDITORIUM
08.30-08.55	SS1	Blue Team and Red Team Approach to Hardware Trust Assessment
		J. Rajendran, R Karri
08.55-09.20	SS2	Circumventing a Ring Oscillator Appraoch to FPGA-Based Hardware Trojan Detection
		J. Rilling, D. Graziano, J. Hitchcock, T. Meyer, X. Wang, P. Jones, J. Zambreno
09.20-09.45	SS3	Hardware Trojans: The Defense and Attack of Integrated Circuits
		T. Reece, W. Robinson
09:45-10:10	SS4	Sequential Hardware Trojan: Side-channel Aware Design and Placement
		X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia
10:10-10:35	SS5	Implementing Hardware Trojans: Experiences from a Hardware Trojan Challenge
		G. T. Becker, A. Lakshminarasimhan, L. Lin, S. Srivathsa, V. B. Suresh, W. Burelson
10:35-11:00	SS6	Is Single-Scheme Trojan Prevention Sufficient?
		Y. Jin, Y. Makris
11:00-11:25	SS7	Red Team: Design of Intelligent Hardware Trojans with Known Defense Schemes
		X. Zhang, N. Tuzzio, M. Tehranipoor
11:25-11:40			COFFEE BREAK
11:40-13:20		Session 7.1 Memories and Caches (Logic and Circuits Track) Session Chair: Amy Novak, AMD	11:40-13:20		Session 7.2 Systems Potpourri (Systems Track) Session Chair: Ann Gordon-Ross, Univ. of Florida
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1
11:40-12:05	8	Evaluation of Issue Queue Delay: Banking Tag RAM and Identifying Correct Critical Path	11:40-12:05	284	Adaptable Architectures for Distributed Visual Target Tracking
	REGULAR	K. Yamaguchi, Y. Kora, H. Ando		REGULAR	D. Forte, A. Srivastava
12:05-12:30	123	A 13T 32nm CMOS Memory Cell for Hardening to a Single Event with Multiple Node Upset	12:05-12:30	172	Improving Robustness of GPUs by Making Use of Faulty Parts
	REGULAR	F. Lombardi, S. Lin, Y. Kim		REGULAR	A. Durytskyy, M. Zahran, R. Karri
12:30-12:55	56	Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology	12:30-12:55	101	Functional Correctness for CMP Interconnects
	REGULAR	F. Moradi, G. Panagopoulos, G. Karakonstantis, D. Wisland, H. Mahmoodi, J. K. Madsen, K. Roy		REGULAR	R. Abdel-Khalek, R. Parikh, A. Deorio, V. Bertacco
12:55-13:20	97	Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors	12:55-13:20	160	Task Model for On-Chip Communication Infrastructure Design for Multicore Systems
	REGULAR	S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio		REGULAR	B. Phanibhushana, K. Ganeshpure, S. Kundu
13:20-14:20			LUNCH
14:20-16:00		Session 8.1 Memory and Cache Architecture (Systems Track) Session Chair: Georgi Gaydadjiev, TU Delft	14:20-16:00		Session 8.2 Reliable and Adaptive Architectures (Architecture Track) Session Chair: Todd Austin, Univ. of Michigan
	PAPER ID	AUDITORIUM		PAPER ID	ROOM 1
14:20-14:45	135	Improving the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory	14:20-14:45	119	CPACT - The Conditional Parameter Adjustment Cache Tuner for Dual-Core Architectures
	REGULAR	G. Sun, E. Kursun, J. Rivers, Y. Xie		REGULAR	M. Rawlins, A. Gordon-Ross
14:45-15:10	28	A Morphable Phase Change Memory Architecture Considering Frequent Zero Values	14:45-15:10	49	SoftBeam: Precise Tracking of Transient Faults and Vulnerability Analysis at Processor Design Time
	REGULAR	M. Arjomand, A. Jadidi, A. Shafiee, H. Sarbazi-Azad		REGULAR	M. Gschwind, V. Salapura, C. Trammell, S. McKee
15:10-15:35	245	An Energy- and Performance-Aware DRAM Cache Architecture for Hybrid DRAM/PCM Main Memory Systems	15:10-15:35	5	ARCc: A Case for an Architecturally Redundant Cache-coherence Architecture for Large Multicores
	REGULAR	H. Lee, S. Baek, C. Nicopoulos, J. Kim		REGULAR	O. Khan, H. Hoffmann, M. Lis, F. Hijaz, A. Agarwal, S. Devadas
15:35-16:00	73	The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System	15:35-16:00	166	Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
	REGULAR	K. Therdsteerasukdi, G. Byun, J. Ir, G. Reinman, J. Cong, F. Chang		REGULAR	P. Subramanyan, V. Singh, K. Saluja, E. Larsson
16:00-16:10			CLOSING by Georgi Gaydadjiev and Sofiene Tahar (AUDITORIUM)
16:10			END OF THE CONFERENCE